In general, in a memory cell array of dynamic RAM (DRAM), as shown in FIG. 5, the bit line pair (bit line/auxiliary bit line) BLi and BLi- are connected to the differential sense amplifier SAi installed at each row or each column, and the memory cells MCi,1, MCi,3, MCi,5, etc., of an odd array are arranged (connected) at an intersection position of the bit line BLi and the odd word lines WL1, WL3, WL5, etc. The memory cells MCi,0, MCi,2, MCi,4, etc., of an even array are arranged (connected) at an intersection of the auxiliary bit line BLi- and the even word lines WL0, WL2, WL4, etc.
Each memory cell MCi,j is constituted by one transistor Qi,j and one capacitor Ci,j. If the word line WLj connected to the memory cell MCi,j is activated, the transistor Qi,j turns On, and the potential information (memory information) of the capacitor Ci,j is input into the sense amplifier SAi via the bit line BLi or the auxiliary bit line BLi-.
FIG. 6 shows a typical circuit constitution of the sense amplifier SAi. In this sense amplifier circuit, the transistors TR1 and TR2 constitute a transfer gate for connecting the bit line pair BLi and BLi-. The transistors TR3, TR4, and TR5 constitute a precharge circuit for precharging the bit line pair BLi and BLi-with the intermediate potential Vcc/2 of a power supply voltage. A pair of p-type MOS transistors TR6 and TR7 and a pair of n-type MOS transistors TR8 and TR9 constitute an amplifying circuit for amplifying a voltage present on a bit line pair respectively. The transistors TR10 and TR11 constitute a transfer gate for optionally connecting the bit line pair BLi and BLi- to the data input and output line pair IO and IO-.
FIG. 7 explains the operation of writing or reading of a data in and out of a memory cell in this memory cell array. In a standby state before reading or writing, the equalizing control signals .phi.E and .phi.F are respectively at H level, and the transistors TR3, TR4, and TR5 turn on. In the precharge feeder BLR, the voltage of Vcc/2 level is given, and both the bit line BLi and the auxiliary bit line BLi- are precharged to the voltage of Vcc/2 level by feeding from the feeder BLR.
If the external low address strobe signal RAS- falls to L level, the equalizing control signals .phi.E and .phi.F go to L level in accordance with this, and the transistors TR3, TR4, and TR5 of the precharge circuit turn off. Next, the word line WLj of an array selected is activated, the potential information of the memory cell MCi,j connected to the word line WLj is read out on one side of a bit line pair, for example, on the auxiliary bit line BLi-, and the potential of the auxiliary bit line BLi- changes. In the example of FIG. 7, the potential information is "0," the potential of the auxiliary bit line BLi- changes from the Vcc/2 level to a slightly lower level while the bit line BLi remains at the Vcc/2 level.
Next, when one sense amplifier drive control signal NC and the other sense amplifier drive control signal PC change to H level and L level respectively, the transistors TR12 and TR13 respectively turn on. Then, one sense amplifier drive line SDN is pulled down to the ground potential Vss, and the other sense amplifier drive line SDP is brought up to the power supply voltage Vcc.
In this example, since the potential of the auxiliary bit line BLi- changes from Vcc/2 level to a lower value, the p-type MOS transistor TR7 turns on. Thus, the bit line BLi is connected to the sense amplifier drive line SDP via the transistor TR7, and the bit line BLi is pulled up to the power supply voltage Vcc. On the other hand, when the transistor TR7 turns On, the n-type MOS transistor TR8 turns on, and the auxiliary bit line BLi- is connected to the sense strobe drive line SDN via the transistor TR8, and the auxiliary bit line BLi- is pulled down to the power supply voltage Vss.
Next, if the Y address line YSi is activated by the Y address decoder (not shown in the figure), the transfer gates TR10 and TR11 turn on, and the bit line BLi and the auxiliary bit line BLi- are connected to the data input and output line IO and the data input and output auxiliary line IO- respectively. Thus, when writing, the data on the data input and output auxiliary line IO- is sent to the auxiliary bit line BLi- via the transfer gate TR11 and the transfer gate TR2 and is written into the memory cell (the memory cell of an intersection position of the auxiliary bit line BLi- and the word line WLj) MCi,j. When reading, the data read from the memory cell MCi,j to the auxiliary bit line BLi- is sent on the data input and output auxiliary line IO- via the transfer gate T2 and the transfer gate T11.
On the other hand, as a bit line arrangement structure for enhancing the degree of integration of a memory cell array, as shown in FIG. 8, one, for example, BLi+1, of a bit line and an auxiliary bit line which compose an adjacent bit line pair is arranged at almost an intermediate position between the bit line, for example, BLi and the auxiliary bit line, for example, BLi-, which compose each bit line pair. As shown in FIG. 9, if the pitch of the bit line contact positions, for example, BCi,c and BCi,c+1 which are adjacent each other on each bit line or auxiliary bit line is assumed to be P, a so-called 1/4 pitch bit line contact system, in which the positions of the bit line contact, for example, BCi,c+1 and BCi+1,c+1 which are adjacent to each other in the array direction (Y direction) of a bit line and an auxiliary bit line is shifted as much as P/4 in the direction parallel with a bit line or auxiliary bit line, is known. In the bit line arrangement structure of this system, an array of the word lines WLj, WLj+1, etc., is assembled in a complicated manner; however, there is an advantage that it can be wired at higher density, compared with an ordinary 1/2 pitch bit line contact system. In FIG. 9, MAi,c, MAi,c+1, etc., are element areas, and MCi,j-2, MCi,j, etc., are memory cells.
In the above-mentioned memory cell array of a DRAM, bit lines and auxiliary bit lines are adjacent to each other or are coupled to each other via a parasitic capacitance. For this reason, during sensing of a bit line or auxiliary bit line, the potential change on another adjacent bit line or auxiliary bit line is affected, and an incorrect sensing (erroneous readout) is likely to occur.
Here, in the above-mentioned 1/4 pitch bit line contact system, as shown in FIG. 10, it is usual to adopt a twisting structure in which bit lines, for example, BL0 and auxiliary bit lines, for example, BL0-, which comprise each odd or even bit line pair (in FIG. 10, even numbers), switch positions with each other by twisting once at almost the intermediate position in the longitudinal direction of a line. According to this twist structure, since the interval between an arbitrary bit line pair (bit line/auxiliary bit line) and another adjacent bit line or auxiliary bit line is symmetric at both sides of the twist part TW, the parasitic capacitance is at equilibrium. Therefore, when the potential changes on this other adjacent bit line or auxiliary bit line, the influences on the bit line and an auxiliary bit line of the bit line pair via the parasitic capacitance are equal to each other and cancel.
However, in this kind of memory cell array, a parasitic capacitance also exists between a bit line pair and the Y select line YS. Each Y select line YS0, YS1, etc., is arranged in parallel with them via an interlayer insulating film on a bit line pair and is commonly connected to one or more (in the example of FIG. 10, four) sense amplifiers. In the example of FIG. 10, it is assumed that a substantial parasitic capacitance exists between the Y select line YS0 and its adjacent bit lines or auxiliary bit lines BL0, BL0-, BL1-, BL2, and BL2-. In this case, in the bit line pair (BL0,BL0-), since the positions of the bit line BL0 and the auxiliary bit line BL0- switch at both sides of the twisting part TW and become symmetric, the parasitic capacitance for the Y select line YS0 is at equilibrium between both. In the bit line pair (BL2,BL2-), similarly, the parasitic capacitance for the Y select line YS0 is also at equilibrium between both.
However, in the bit line pair (BL1, BL1- ), since the bit auxiliary line BL1- is positioned immediately below the Y select line YS0, while the bit line BL1 is positioned at the side of the Y select line YS0, the parasitic capacitance for the Y select line YS0 is not at equilibrium between both.
Therefore, for example, in case writing or reading is carried out for the memory cell MC1,j on the auxiliary bit line BLi-, as shown in FIG. 11, the potential of the Y select line YS0 rises to Vcc (H level), its potential change functions nonequilibratorily or nonuniformly via a parasitic capacitance to the bit line pair (BL1,BL1-), and as shown in the dotted lines (BLI',BLI-'), the potential on the bit line pair (BL1,BL1-) is disordered. If this disorder is large, the potential of the bit line pair (BL1,BL1-) is reversed, and the data read out of the memory cell MC1,j is likely to be corrupted.
Thus, in the past, the problem of incorrect sensing due to a parasitic capacitance existing between a bit line pair and a select line was not solved.
It is an object of the present invention to provide a semiconductor memory device which can sense the memory information from a memory cell in a stable, reliable fashion by balancing a parasitic capacitance existing between a select line and its adjacent bit line pair as well as a parasitic capacitance existing between bit lines and auxiliary bit lines that are adjacent each other, or a bit line and auxiliary bit line.